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CMOS logic circuit optimum design for radiation tolerance

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2 Author(s)
H. Hatano ; Toshiba Corporation, Semiconductor Device Engineering Laboratory, Kawasaki, Japan ; M. Shibuya

CMOS logic circuit optimum design for radiation tolerance has been investigated, based on NMOS and PMOS transistor parameter shift data due to radiation effects. The DC noise immunity for the three-input NAND has been found to be 36% greater than for the three-input NOR. The gate area for the optimised NAND is about three times smaller than that for the optimised NOR.

Published in:

Electronics Letters  (Volume:19 ,  Issue: 23 )