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Yield enhancement of bit level systolic array chips using fault tolerant techniques

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2 Author(s)
McCanny, J.V. ; Royal Signals & Radar Establishment, Great Malvern, UK ; McWhirter, J.G.

Methods by which bit level systolic array chips can be made fault tolerant are discussed briefly. Using a simple analysis based on both Poisson and Bose-Einstein statistics we demonstrate that such techniques can be used to obtain significant yield enhancement. Alternatively, the dimensions of an array can be increased considerably for the same initial (nonfault tolerant) chip yield.

Published in:

Electronics Letters  (Volume:19 ,  Issue: 14 )