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Fast hardware implementation of the Winograd Fourier transform algorithm

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2 Author(s)
M. D. Macleod ; Cambridge Consultants Ltd., Cambridge, UK ; N. L. Bragg

We describe a novel partitioning of small Winograd DFTs into two identical subunits, each of which computes a real-input DFT. A bit-serial arithmetic single IC implementation in semicustom or custom LSI is described. A fast hardware WFTA is then proposed which is efficient for complex or real input data.

Published in:

Electronics Letters  (Volume:19 ,  Issue: 10 )