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Implementation of convolution and Fourier transforms using 1-bit systolic arrays

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2 Author(s)
Ward, J.S. ; University of Durham, Department of Applied Physics & Electronics, Durham, UK ; Stanier, B.J.

The use of systolic arrays of 1-bit cells to implement circular convolution and DFTs is described. The architecture is very well suited to VLSI implementation. It is shown that considerable simplification of the architecture is possible for real-valued DFTs.

Published in:

Electronics Letters  (Volume:18 ,  Issue: 18 )