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A clock recovery circuit has been constructed using dual-gate MESFETs. From a 5 Gbit/s data stream consisting of 50 time division multiplexed 100 MHz channels, the 100 MHz master clock is recovered both in frequency and in phase. Phase jitter is less than 20 ps in the presence of data and channel noise. A significant advantage of this approach over previous ones is the simplicity in the clock recovery circuitry and in demultiplexing individual channels. This permits easy speed upgrading to beyond 10 Gbit/s.