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Integrated tapped MOS analogue delay line using switched capacitor technique

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3 Author(s)
Enomoto, T. ; Nippon Electric Co. Ltd., Basic Technology Research Laboratories, Kawasaki, Japan ; Ishihara, T. ; Yasumoto, Masa-Aki

A tapped MOS analogue delay line based on the switched capacitor technique for realisation of low-power analogue LSIs is fabricated using a VLSI process. Excellent characteristics such as large signal handling capability, low total harmonic distortion of ¿85 dB for 3V(p-p) input and fast operation speed of more than 1 MHz clock rate with negligible charge transfer loss are obtained.

Published in:

Electronics Letters  (Volume:18 ,  Issue: 5 )