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Planar GaAs normally-off j.f.e.t. for high speed logic circuits

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4 Author(s)
Kato, Y. ; Sony Corporation, Research Center, Yokohama, Japan ; Dohsen, M. ; Kasahara, J. ; Watanabe, N.

Planar GaAs j.f.e.t.s in the normally-off mode were fabricated by direct selective ion implantation into a semi-insulating Cr-doped substrate for n-type active regions and selective Zn diffusion for p-type gate areas. The p-n junction gate, typically 2 ¿m in length and 20 ¿m in width, was formed without appreciable anomalous lateral diffusion. A 15-stage ring oscillator formed with resistor-f.e.t. logic gates exhibited a propagation delay time of 73 ps per stage with a power-delay product of 320 fJ. The minimum power-delay product was 5.6 fJ with delay time of 163 ps.

Published in:

Electronics Letters  (Volume:16 ,  Issue: 21 )