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Designing synchronous circuits with partial asynchronous operation using clocked flip-flops with d.c. inputs

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2 Author(s)
Dervisoglu, B.I. ; University of Edinburgh, Department of Computer Science, Edinburgh, UK ; Sholl, H.A.

A practical design technique is developed that takes advantage of four inputs, J, K, S and R, often available on flip-flops to design circuits involving both synchronous and asynchronous behaviour. A compact state-table representation is described, along with the requirements for state reduction, assignment and circuit realisation. The technique can produce a saving in logic complexity over completely asynchronous designs.

Published in:

Electronics Letters  (Volume:10 ,  Issue: 14 )

Date of Publication:

July 11 1974

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