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Placement algorithm for logic modules

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1 Author(s)
Kazuhiro, Ueda ; NTT, Integrated Circuit Section, Musashino Electrical Communication Laboratory, Musashino, Japan

The letter presents a placement algorithm that is based on the concepts of assuming an attractive force by `friendly components¿ and a repulsive force by `unfriendly components¿ and then allocating each component on a position balanced by these two opposite forces. This algorithm has some prominent features over conventional relaxation (or gravitational) methods.

Published in:

Electronics Letters  (Volume:10 ,  Issue: 10 )