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Comment on the speed of binary multiplication using cellular arrays

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2 Author(s)
J. C. Majithia ; University of Waterloo, Department of Electrical Engineering, Waterloo, Canada ; K. H. Siemens

A known recoding algorithm is considered and is shown to yield a speed improvement of approximately 33% for serial multiplication. However, in the case of cellular-array multipliers, such a recoding appears to offer no advantage; instead, it may even result in a speed penalty owing to the sequential nature of the recoding algorithm.

Published in:

Electronics Letters  (Volume:7 ,  Issue: 15 )