By Topic

Low-Power Dual-Microphone Speech Enhancement Using Field Programmable Gate Arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Halupka, D. ; Univ. of Toronto, Toronto ; Rabi, A.S. ; Aarabi, P. ; Sheikholeslami, A.

This paper discusses two implementations of a dual-microphone phase-based speech enhancement technique. The implementations compared are based on a field-programmable gate array (FPGA) and a digital signal processor (DSP). The time-varying, frequency-dependent, phase-difference between each incoming sound signal is used to mask each respective frequency, thereby reducing noise by minimizing the contributions of signal frequency components that have a low signal-to-noise ratio (SNR). Phase-based filtering can achieve high SNR gains with just two microphones, making it ideal for small devices that lack the room for a multimicrophone array. Moreover, these devices often have a limited battery life and lack the processing power needed for software-based speech enhancement. This paper presents an FPGA-based dual-microphone speech enhancement implementation, which was designed specifically for low-power operation. This implementation is compared with an off-the-shelf DSP implementation, with respect to processing capabilities and power utilization.

Published in:

Signal Processing, IEEE Transactions on  (Volume:55 ,  Issue: 7 )