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This paper discusses two implementations of a dual-microphone phase-based speech enhancement technique. The implementations compared are based on a field-programmable gate array (FPGA) and a digital signal processor (DSP). The time-varying, frequency-dependent, phase-difference between each incoming sound signal is used to mask each respective frequency, thereby reducing noise by minimizing the contributions of signal frequency components that have a low signal-to-noise ratio (SNR). Phase-based filtering can achieve high SNR gains with just two microphones, making it ideal for small devices that lack the room for a multimicrophone array. Moreover, these devices often have a limited battery life and lack the processing power needed for software-based speech enhancement. This paper presents an FPGA-based dual-microphone speech enhancement implementation, which was designed specifically for low-power operation. This implementation is compared with an off-the-shelf DSP implementation, with respect to processing capabilities and power utilization.