By Topic

Calculation method to obtain worst-case static noise margins of logic circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Lohstroh, J. ; Philips Research Laboratories, Eindhoven, Netherlands

A relatively simple calculation method is introduced using the flip-flop method, and by using the criterion that, with marginal static noise applied to the flip-flop, the loopgain is 1. As an example, the worst-case static series voltage noise margin of I2L is calculated.

Published in:

Electronics Letters  (Volume:16 ,  Issue: 8 )