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The increased flexibility offered by FPGAs implies that more transistors are needed which leads to higher power consumption per logic gate. FPGAs power consumption is fast becoming an essential design consideration especially for mobile systems with a limited power supply. The effect of components' region-constrained placement on reducing internal nets total capacitance and the corresponding change in internal nets' total dynamic power consumption is investigated. Two logic circuits were specified as components covering around 80% of total FPGA busy gates. These components are multiplexers and adders along with multipliers. Each of these components was implemented on two of Xilinx FPGA 's families, namely; Spartan II and Virtex. Gate- level power estimation for different region-constrained placements of each logic circuit was carried out using the Xilinx hierarchal power distribution analyzer, XPower.