Referenced Items are not available for this document.
A feasibility study for implementing the AES encryption algorithm in hardware achieving 500 Gbits/s is presented. The methodology followed in the process of obtaining the solution allowed us to reach a highly regular solution that is scalable.
Published in:
Microelectronics, 2006. ICM '06. International Conference on
Date of Conference: 16-19 Dec. 2006
- Page(s):
- 190 - 193
- E-ISBN :
- 1-4244-0765-6
- Print ISBN:
- 1-4244-0764-8
- INSPEC Accession Number:
- 10289991
- Conference Location :
- Dhahran
- Digital Object Identifier :
- 10.1109/ICM.2006.373299
- Product Type:
- Conference Publications
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