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An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration

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7 Author(s)

An 11 b 800MS/S time-interleaved ADC is implemented in a 90nm CMOS process for a 10GBase-T application. A single open-loop T/H circuit using a cascode source follower achieves high resolution and conversion rate. The offset and gain mismatches are corrected by the digital background calibration. The measured DNL and INL are <0.5LSB and <1.6LSB, respectively. The measured SNDRs are 58 and 54dB for 15 and 400MHz inputs, respectively. The 1.4mm2 ADC consumes 350mW from a 1.3V supply (1.5V for T/H).

Published in:

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Date of Conference:

11-15 Feb. 2007

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