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A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS

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5 Author(s)
Young-Deuk Jeon ; Electron. & Telecommun. Res. Inst., Daejeon ; Seung-Chul Lee ; Kwi-Dong Kim ; Jong-Kee Kwon
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A 4.7mW 10b 30MS/s pipelined ADC is implemented without a front-end S/H for low power consumption and small area. The prototype ADC, fabricated in a 90nm CMOS process, shows an SNDR of 58.4dB and an SFDR of 75.2dB with a 2MHz sinusoidal input sampled at 30MS/S. The 0.32 mm2 chip dissipates 4.7mW at a 1V supply and has a FOM of 0.23pJ/conversion-step.

Published in:

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Date of Conference:

11-15 Feb. 2007