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A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy

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2 Author(s)
Verma, N. ; Massachusetts Inst. of Technol., Cambridge, MA ; Chandrakasan, A.P.

A 65nm 256kb 8T SRAM operates in sub-V, at 350mV. Peripheral assists eliminate sub-V, bitline leakage without limiting read current, and for a given area, sense-amplifier redundancy reduces read errors from offsets by a factor of five compared with device upsizing.

Published in:

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Date of Conference:

11-15 Feb. 2007

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