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A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability

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3 Author(s)
Kaeriyama, S. ; NEC, Sagamihara ; Kajita, M. ; Mizuno, M.

A clock generator fabricated in 90nm CMOS occupies 300times128mum2 die area and dissipates 40mW at 1.2V. An interleaved clock-edge control technique extends the frequency tuning range and enables control of both rising and falling edge timing. A clock-period dithering technique enhances frequency tuning resolution. Disturbance-control functions that control jitter, duty cycle, and clock skew make timing margin testing possible

Published in:

Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International

Date of Conference:

11-15 Feb. 2007