A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability

A clock generator fabricated in 90nm CMOS occupies 300times128mum² die area and dissipates 40mW at 1.2V. An interleaved clock-edge control technique extends the frequency tuning range and enables control of both rising and falling edge timing. A clock-period dithering technique enhances frequency tuning resolution. Disturbance-control functions that control jitter, duty cycle, and clock skew make timing margin testing possible