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An SoC is presented with dual 2GHz Powertrade cores, coherent crossbar interconnect, 2MB L2 cache, and memory and I/O subsystem. The chip consumes a maximum of 25W of power. The 115mm2 die is implemented in a 65nm 8M process with low-power design techniques. Circuits to improve system performance under power constraints are discussed
Published in:
Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International
Date of Conference: 11-15 Feb. 2007
- Page(s):
- 104 - 105
- ISSN :
- 0193-6530
- E-ISBN :
- 1-4244-0853-9
- Print ISBN:
- 1-4244-0853-9
- INSPEC Accession Number:
- 9507920
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ISSCC.2007.373609
- Product Type:
- Conference Publications
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