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Circuit Performance of Low-Power Optimized Multi-Gate CMOS Technologies

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8 Author(s)
K. Schruefer ; Infineon Technologies, 81726 Munich, Germany, phone: +49 89 234 86618, klaus.schruefer@infineon.com ; K. von Arnim ; C. Pacha ; J. Berthold
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A multi-gate CMOS technology for low-power applications with highly competitive digital performance is presented. Ring oscillators with metal gates and undoped fins are measured with high yield demonstrating the capability of large scale integration. An inverter delay of 15 ps and 0.5 nA/stage off-current at Vdd=1.2 V shows an improved leakage-performance trade-off compared to 65 nm low-standby power CMOS technologies. Scalability to 32 nm and beyond is shown.

Published in:

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

Date of Conference:

23-25 April 2007