Referenced Items are not available for this document.
In this paper the voltage scaling of embedded non-volatile memories was discussed. Floating gate cells with high-K IPD and nitride trapping cells with high-K tunnel and blocking layers offer significant reduction of the program/erase efficiency. A major voltage reduction could be achieved by using phase change memory technology that is a serious contender for charge based embedded non-volatile memories in advanced sub-50 nm CMOS nodes. This paper also discusses experimental results, possibilities and challenges of memories to enable low voltage/power operation.
Published in:
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on
Date of Conference: 23-25 April 2007
- Page(s):
- 1 - 2
- ISSN :
- 1930-885X
- E-ISBN :
- 1-4244-0585-8
- Print ISBN:
- 1-4244-0585-8
- INSPEC Accession Number:
- 9705868
- Conference Location :
- Hsinchu
- Digital Object Identifier :
- 10.1109/VTSA.2007.378932
- Product Type:
- Conference Publications
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