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A 3D Packaging Technology for High-Density Stacked DRAM

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1 Author(s)
Masaya Kawano ; Advanced Device Development Division, NEC Electronics, 1120, Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan

A 3D packaging technology has been developed for high-density stacked DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using the so-called SMAFTI technology. A new bump and wiring structure for feedthrough interposer (FTI) has also been developed for fine-pitch and low-cost bonding.

Published in:

2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

Date of Conference:

23-25 April 2007