Referenced Items are not available for this document.
A 3D packaging technology has been developed for high-density stacked DRAM. Highly-doped poly-Si through-silicon vias (TSVs) are used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM compatible process. Through optimization of the process conditions and layout design, fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using the so-called SMAFTI technology. A new bump and wiring structure for feedthrough interposer (FTI) has also been developed for fine-pitch and low-cost bonding.
Published in:
VLSI Technology, Systems and Applications, 2007. VLSI-TSA 2007. International Symposium on
Date of Conference: 23-25 April 2007
- Page(s):
- 1 - 2
- ISSN :
- 1930-885X
- E-ISBN :
- 1-4244-0585-8
- Print ISBN:
- 1-4244-0585-8
- INSPEC Accession Number:
- 9705861
- Conference Location :
- Hsinchu
- Digital Object Identifier :
- 10.1109/VTSA.2007.378921
- Product Type:
- Conference Publications
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