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Novel Configurable Architecture of ML-Decomposed Binary Arithmetic Encoder for Multimedia Applications

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3 Author(s)
Yu-Jen Chen ; Nat. Taiwan Univ., Taipei ; Chen-Han Tsai ; Liang-Gee Chen

A novel architecture of ML-decomposed binary arithmetic coder is proposed. Through the analysis of previous designs, the traditional processing unit is divided into two parts, MPS encoder and LPS encoder. With different arrangements of these two basic components, we develop two types of ML-decomposed structures. To increase the throughput of arithmetic coding, ML cascade architecture puts the coders in serial, while throughput-selection architecture offers several choices in parallel. Their design methodologies are described in this paper. Both methods achieve very high throughput, more than 800 M symbols/sec. And they are configurable and extensible to supply a wide range of specifications. Moreover, the proposed architecture can be used in binary arithmetic coding of various video and image standards.

Published in:

VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on

Date of Conference:

25-27 April 2007