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A Power-Saved 1Gbps Irregular LDPC Decoder based on Simplified Min-Sum Algorithm

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4 Author(s)
Qi Wang ; Production & Syst. Waseda Univ., Kitakyushu ; Shimizu, K. ; Ikenaga, T. ; Goto, S.

In this paper we proposed a fully-parallel irregular LDPC decoder which uses only registers to store the temporary intrinsic messages. Our decoder adopts a simplified min-sum algorithm to reduce the hardware implementation complexity and area, and due to the factor modification we achieve a negligible performance loss compared with the general min-sum algorithm. Considering reducing the power consumption, we also propose a power-saved strategy according to which the message evolution will halt as the parity-check condition is satisfied. This strategy will save us higher than 50% power under good channel condition. The synthesis result in 0.18 mum CMOS technology shows our decoder for (648,540) irregular LDPC code achieves high throughput (1 Gbps) with 9.0 ns latency.

Published in:

VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on

Date of Conference:

25-27 April 2007

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