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Steady-State Analysis of Phase-Locked Loops Using Binary Phase Detector

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4 Author(s)
Shanfeng Cheng ; Texas A&M Univ., College Station ; Haitao Tong ; Silva-Martinez, J. ; Karsilayan, A.I.

Phase-locked loops (PLLs) using binary phase detectors (BPDs) are modeled and analyzed in this paper. Steady-state behavior for PLLs based on BPDs (BPLs) using first- and second- order loop filters is characterized using transient waveform equations. It is shown that BPLL has a range of oscillation modes in steady state when there is no input jitter. The BPLL is most likely to operate at the most stable oscillation mode (MSOM) under the disturbance of random input jitter. The MSOM is determined by evaluating the relative stability of all the modes. The expected value of the output jitter amplitude is derived and its dependence on the loop parameters is analyzed.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 6 )