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Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers

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2 Author(s)
Alioto, M. ; Siena Univ., Siena ; Palumbo, G.

In this brief, a design strategy to minimize the delay of high-fan-in CMOS multiplexers (MUXes) based on the heterogeneous-tree approach is proposed. A preliminary circuit analysis is carried out that takes interconnect parasitics into account, and analytical design criteria are then derived by assuming that the MUX switches are made up of pass transistors or transmission gates, as is often done in practical cases. The design criteria turn out to be very simple (even more than those in [1] which did not consider the effect of interconnects) and independent of the adopted technology. In addition, an approximate delay expression is given to predict the achievable speed performance before actually carrying out the optimized design. The results are validated through post-layout simulations on a 90-nm CMOS process.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 6 )