By Topic

Using the Cell Processor As a Network Assist to Minimize Latency

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Khunjush, F. ; Univ. of Victoria, Victoria ; Dimopoulos, N.J.

The main contributors to message delivery latency in message passing environments are the copying operations needed to transfer and bind a received message to the consuming process/thread. A significant portion of the software communication overhead is attributed to message copying. Recently, a set of factors, such as poor performance/power efficiency and limited design scalability in monolithic designs, has been leading high-performance processor architectures toward designs that feature multiple processing cores on a single chip (a.k.a. CMP). In this work we study and quantify the latency of different techniques to facilitate the receiving and binding the arrived data in message passing applications running on a cell processor, which is an asymmetric chip-multiprocessors.

Published in:

Electrical and Computer Engineering, 2007. CCECE 2007. Canadian Conference on

Date of Conference:

22-26 April 2007