By Topic

Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Jun Cheng Chi ; Chung Yuan Christian Univ., Chung-li ; Hung Hsie Lee ; Sung Han Tsai ; Mely Chen Chi

We propose a multiple supply voltage scaling algorithm for low power designs. The algorithm combines a greedy approach and an iterative improvement optimization approach. In phase I, it simultaneously scales down as many gates as possible to lower supply voltages. In phase II, a multiple way partitioning algorithm is applied to further refine the supply voltage assignment of gates to reduce the total power consumption. During both phases, the timing correctness of the circuit is maintained. Level converters (LCs) are adjusted correctly according to the local connectivity of the different supply voltage driven gates. Experimental results show that the proposed algorithm can effectively convert the unused slack of gates into power savings. We use two of the ISPD2001 benchmarks and all of the ISCAS89 benchmarks as test cases. The 0.13-mum CMOS TSMC library is used. On average, the proposed algorithm improves the power consumption of the original design by 42.5% with a 10.6% overhead in the number of LCs. Our study shows that the key factor in achieving power saving is including the most comfortable supply voltage in the scaling process.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:15 ,  Issue: 6 )