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Reconfigurable computing has a recognized potential in processor design. It provides a middle trade-off between speed and flexibility. It provides performance close to application-specific-hardware, yet preserves the general-purpose-processor flexibility. This paper presents the mapping and performance analysis of the implementation of the lookup table for two encryption algorithms, namely Rijndael and Twofish, on a coarse grain dynamic reconfigurable platform, namely MorphoSys. MorphoSys is a dynamic reconfigurable architecture targeted for computer intensive applications with parallel nature. Since the MorphoSys does not support the indirect addressing, we present in this paper a methodology to implement an alternative. We present the details of the mapping of the two lookup tables with thorough analysis. The methodology we used can be utilized in other Memoryless systems. Finally, an instruction set extension was proposed to enhance the performance.