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The research on security issues is getting more important, as the number of embedded and networked computing systems is constantly increasing. Due to strict restrictions and strong requirements, only special software applications can be used in security-critical embedded systems. So, it is necessary to secure those software applications with a special hardware implementation of a secure processor architecture. In this paper, we propose the architecture of the Secure CPU, including a memory structure using the SecureTag technique for marking memory lines. Our basic idea was to extend CPU registers by two replicas, which represent the lowest and highest value of a particular register. The advantages of this concept are minor changes in the architecture, the permanent and implicit checking of bounds, the secure storage of bounds in the memory and the high compatibility to several software applications. We verified our concept with an adapted processor simulator and describe its adaptations.