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Hardware/Firmware Verification of Graphic IP

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1 Author(s)
Romain, K. ; STMicroelectronics, Grenoble

This paper describes methods and simulation techniques used to verify the functional correctness of a flexible video processing engine IP. The verification environment relies on co-simulation of the RTL IP under-design with functional building blocks, developed using SystemC constructs. We try here to assess a number of problems encountered during the verification of complex IPs such as flexibility of functions, simulation speed and performance.

Published in:

Rapid System Prototyping, 2007. RSP 2007. 18th IEEE/IFIP International Workshop on

Date of Conference:

28-30 May 2007