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Optimization of Area and Performance by Processor-Like Reconfiguration

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3 Author(s)
Tobias Oppold ; Department of Computer Engineering, University of Tuebingen, Sand 13, 72076 Tuebingen, Germany. ; Sven Eisenhardt ; Wolfgang Rosenstiel

It is well known that the area efficiency of a digital circuit can be improved by reconfiguration due to the reuse of resources. In this paper, we show that this benefit can be achieved for a wide range of applications if the reconfiguration can take place within each clock cycle, and we quantify the benefit by area estimations from a synthesizable architecture model. Although reconfiguration typically involves a decrease of performance, we show how performance can actually be increased by redirecting communication through the time domain. This increase is quantified by estimations from a silicon-proven commercial architecture and its associated compiler.

Published in:

2007 IEEE International Parallel and Distributed Processing Symposium

Date of Conference:

26-30 March 2007