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Power-Aware Bandwidth-Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems

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2 Author(s)
Kodi, A.K. ; Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ ; Louri, A.

As communication distances and bit rates increase, opto-electronic interconnects are becoming de-facto standard/or designing high-bandwidth low-latency interconnection networks for high performance computing (HPC) systems. While bandwidth scaling with efficient multiplexing techniques (wavelengths, time and space) are available, static assignment of wavelengths can be detrimental to network performance for adversial traffic patterns. Dynamic bandwidth reconfiguration based on actual traffic pattern can lead to improved network performance by utilizing idle resources. While dynamic bandwidth re-allocation (DBR) techniques can alleviate interconnection bottlenecks, power consumption also increases considerably. In this paper, we propose a dynamically re configurable architecture called E-RAPID (extended-reconfigurable, all-photonic interconnect for distributed and parallel systems) that not only dynamically reallocates bandwidth, but also reduces the power consumption for all traffic patterns. Our proposed LS (lock-step) reconfiguration technique combines dynamic power management (DPM) with DBR techniques, achieving a reduction in power consumption of 25%-50% while degrading the throughput by less than 5%.

Published in:

Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International

Date of Conference:

26-30 March 2007