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Keynote Speech: Avoiding the Memory Bottleneck through Structured Arrays

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1 Author(s)
Flynn, Michael J. ; Stanford University

Basic to parallel program speedup is dealing with memory bandwidth requirements. One solution is an architectural arrangement to stream data across multiple processing elements before storing the result in memory. This MISD type of configuration provides multiple operations per data item fetched from memory. One realization of this streamed approach uses FPGAs. We'll discuss both the general memory problem and some results based on work at Maxeler using FPGAs for acceleration.

Published in:

Parallel and Distributed Processing Symposium, 2007. IPDPS 2007. IEEE International

Date of Conference:

26-30 March 2007