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On the 6T-SRAM Cells Degradation Characterization in Ultra-Scaled CMOS Technologies

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3 Author(s)
Nowak, E. ; STMicroelectronics, Crolles ; Denais, M. ; Gierczynski, N.

The large number of reliability challenges in stand-alone MOS transistors publications in last decades IRPS conferences put forward the difficulty to make high quality, low cost and reliable process transistor. A large work has been done at transistor level, and it is now interesting to verify experimentally the link between transistors degradation and circuit performance decrease. The 6T-SRAM cell has been chosen since its performances are directly impacted by negative bias temperature instability (NBTI) and hot carrier injection (HCI) degradation (Li, 2005)

Published in:

Reliability physics symposium, 2007. proceedings. 45th annual. ieee international

Date of Conference:

15-19 April 2007