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Design of High-Voltage-Tolerant Power-Rail ESD Clamp Circuit in Low-Voltage CMOS Processes

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4 Author(s)
Ming-Dou Ker ; Inst. of Electron., National Chiao-Tung Univ., Hsinchu ; Chang-Tzu Wang ; Tien-Hao Tang ; Kuan-Cheng Su

A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1timesVDD devices for 3timesVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mum CMOS process with only 1.2-V devices.

Published in:

Reliability physics symposium, 2007. proceedings. 45th annual. ieee international

Date of Conference:

15-19 April 2007