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Binary Turbo Coding with Interblock Memory

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4 Author(s)
Chia-Jung Yeh ; Graduate Inst. of Commun. Eng., National Taiwan Univ., Taipei ; Yeong-Luh Ueng ; Mao-Chao Lin ; Ming-Che Lu

We investigate the performance of binary codes T constructed from turbo coding with interblock memory. The encoding of T is implemented by serially concatenating a multiplexer, a multilevel delay processor, and a signal mapper to the encoder of a conventional binary turbo code C. With such a construction, in T, there is some irregularity for the code bits in C. To provide more variety of irregularity, we can construct TC which is obtained by passing only a fraction of C through a multilevel delay processor and a signal mapper. We propose iterative decoding between adjacent codewords (IDAC), which provides error performance much better than the iterative decoding within a single codeword (IDSC). Simulation shows that T can have a lower error floor than C for either short or long code length. In some cases, TC can provide better error floors and waterfall regions than C.

Published in:

2007 IEEE Wireless Communications and Networking Conference

Date of Conference:

11-15 March 2007