By Topic

A Transaction Level Modeling of Network-on-Chip Architecture for Energy Estimation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Anh-Vu Dinh-Duc ; HCMC Univ. of Technol., Ho Chi Minh City ; Vivet, P. ; Clouard, A.

The specification on power consumption of a digital system is extremely important due to the growing relevance of the market of portable devices and must be taken into account since the early phases of a complex system-on-chip (SoC) design. Transaction level models for SoC are gaining increasing attention with emerging architectural modeling standards like SystemC. In this paper a transaction level modeling of asynchronous network-on-chip (NOC) architecture is presented. This modeling enables early system-level validation of circuit as well as energy evaluation of circuit, which will have important impact on high-level design decisions.

Published in:

Research, Innovation and Vision for the Future, 2007 IEEE International Conference on

Date of Conference:

5-9 March 2007