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A Transaction Level Modeling of Network-on-Chip Architecture for Energy Estimation

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3 Author(s)
Anh-Vu Dinh-Duc ; HCMC University of Technology, HoChiMinh city, Vietnam, ; Pascal Vivet ; Alain Clouard

The specification on power consumption of a digital system is extremely important due to the growing relevance of the market of portable devices and must be taken into account since the early phases of a complex system-on-chip (SoC) design. Transaction level models for SoC are gaining increasing attention with emerging architectural modeling standards like SystemC. In this paper a transaction level modeling of asynchronous network-on-chip (NOC) architecture is presented. This modeling enables early system-level validation of circuit as well as energy evaluation of circuit, which will have important impact on high-level design decisions.

Published in:

Research, Innovation and Vision for the Future, 2007 IEEE International Conference on

Date of Conference:

5-9 March 2007