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Fast-locking CDR circuit with autonomously reconfigurable mechanism

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3 Author(s)
Woo, J.-K. ; Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul ; Jeong, D.K. ; Kim, S.

A new fast-locking scheme is applied to a clock and data recovery (CDR) circuit based on a phase-locked loop. Locking time is reduced by using an autonomously reconfigurable charge pump and loop filter. A 1.25 Gbit/s prototype CDR circuit has been implemented in a 0.18 mum CMOS technology.

Published in:

Electronics Letters  (Volume:43 ,  Issue: 11 )

Date of Publication:

May 24 2007

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