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Comb Architectures for Finite Field Multiplication in F(2^m)

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3 Author(s)
Namin, A.H. ; Windsor Univ., Windsor ; Huapeng Wu ; Ahmadi, M.

Two high-speed bit-serial word-parallel or comb-style finite field multipliers are proposed in this paper. The first proposal utilizes a redundant representation for any binary field and the other uses a reordered normal basis for the binary field where a type-II optimal normal basis exists. The proposed redundant representation architecture has a smaller critical path delay compared to the previous methods while the complexities remain about the same. The proposed reordered normal basis multiplier has a significantly smaller critical path delay compared to the previous methods using the same basis or normal basis. Field-programmable gate array (FPGA) implementation results of the proposed multipliers are compared to those of the previous methods using the same basis, which confirms that the proposed multipliers allow a much higher clock rate.

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Computers, IEEE Transactions on  (Volume:56 ,  Issue: 7 )