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Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams

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4 Author(s)
Homma, N. ; Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai ; Degawa, K. ; Aoki, T. ; Higuchi, T.

This paper presents a novel approach to designing multiple-valued arithmetic circuits based on a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). By using CTDs, we can derive possible variations of addition algorithms in a systematic way without using specific knowledge about underlying arithmetic fundamentals. For any weighted number system, we can design the optimal adder structure by trying every possible CTD representation. In this paper, the potential of the CTD- based method is demonstrated through an experimental design of the Redundant-Binary (RB) adder in multiple-valued current-mode logic. We successfully obtained the RB adder that achieves about 32-57% higher performance in terms of power-delay product compared with the conventional designs.

Published in:

Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on

Date of Conference:

13-16 May 2007