By Topic

Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Aditya Bansal ; Purdue Univ., West Lafayette ; Saibal Mukhopadhyay ; Kaushik Roy

In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall offset spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. With the source/drain extension doping controlled at the outer edges of the spacer, the thickness of the spacer determines the channel length. Optimization reduces the sensitivity of the device threshold voltage to the fluctuations in silicon thickness (by 32%) and gate length (by 73%). Our analysis shows that optimization of spacer thickness results in 65% reduction in SRAM cell leakage and improves cell read-failure probability (by 200 X) compared to conventional FinFET SRAM. Access time of an SRAM cell designed with optimized devices is comparable to conventional SRAM. We also compared the optimized-spacer-thickness SRAM cell with one designed using longer gate length and minimum-spacer-thickness transistors. The long-channel-device-based SRAM cell is marginally robust than optimized SRAM; however, increased gate-edge direct-tunneling leakage and parasitic capacitances degrade the power consumption and access time.

Published in:

IEEE Transactions on Electron Devices  (Volume:54 ,  Issue: 6 )