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Return Path Assumption Validation for Inductance Modeling in Digital Design

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5 Author(s)
David, L. ; STMicroelectron., Crolles ; Cregut, C. ; Huret, F. ; Quere, Y.
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Inductance modeling for on-chip interconnects in a typical digital environment is proposed. Regarding the effective loop inductance computation, the issue of current return path assumptions is first discussed. Then, sensible assumptions about the return path localization are presented and systematically validated. Finally, representative structure models allowing prelayout effective inductance estimations are suggested.

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Advanced Packaging, IEEE Transactions on  (Volume:30 ,  Issue: 2 )