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In this paper, a design-for-testability (DFT) technique to test open defects in otherwise undetectable faulty branches in fully static CMOS latches and flip-flops is proposed. The main benefits of our proposal are: 1) it is able to detect a parametric range of resistive opens defects and 2) the performance degradation is very low. The testability of the added DFT circuitry is also addressed. The cost of the proposed technique in terms of speed degradation, area overhead, and extra pins is analyzed. Comparison with other previously proposed testable latches is carried out. Circuits with the proposed technique have been designed and fabricated. Good agreement is observed between the analytical analysis, simulations and experimental measures performed on the fabricated circuits.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:15 , Issue: 5 )
Date of Publication: May 2007