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Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions

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3 Author(s)
Verma, S. ; Dept. of Comput. Sci., California Irvine Univ., CA ; Harris, I.G. ; Ramineni, K.

As an industrial practice, the functional coverage models are developed based on a high-level specification of the design under verification (DUV). However, in the course of implementation a designer makes specific choices which may not be reflected well in a functional coverage model developed entirely from a high-level specification. We present a method to automatically generate implementation-aware coverage models based on the static analysis of a HDL description of the DUV. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design

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Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07

Date of Conference:

16-20 April 2007

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