By Topic

Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Shireesh Verma ; Department of Computer Science, University of California Irvine, Irvine, CA 92697, USA, ; Ian G. Harris ; Kiran Ramineni

As an industrial practice, the functional coverage models are developed based on a high-level specification of the design under verification (DUV). However, in the course of implementation a designer makes specific choices which may not be reflected well in a functional coverage model developed entirely from a high-level specification. We present a method to automatically generate implementation-aware coverage models based on the static analysis of a HDL description of the DUV. Experimental results show that the functional coverage models generated using our technique correlate well with the detection of randomly injected errors into a design

Published in:

2007 Design, Automation & Test in Europe Conference & Exhibition

Date of Conference:

16-20 April 2007