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A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy

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6 Author(s)
A. Milidonis ; VLSI Design Lab., Electrical & Computer Engineering Department, University of Patras, Rio, Greece, e-mail: ; N. Alachiotis ; V. Porpodas ; H. Michail
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This paper present a decoupled architecture of processors with a memory hierarchy of only scratch-pad memories, and a main memory. The decoupled architecture also exploits the parallelism between address computation and processing the application data. The application code is split in two programs the first for computing the addresses of the data in the memory hierarchy and the second for processing the application data. The first program is executed by one of the decoupled processors called Access which uses compiler methods for placing data in the memory hierarchy. In parallel, the second program is executed by the other processor called Execute. The synchronization of the memory hierarchy and the Execute processor is achieved through simple handshake protocol. The Access processor requires strong communication with the memory hierarchy which strongly differentiates it from traditional uniprocessors. The architecture is compared in performance with the MIPS IV architecture of SimpleScalar and with the existing decoupled architectures showing its higher normalized performance. Experimental results show that the performance is increased up to 3.7 times. Compared with MIPS IV the proposed architecture achieves the above performance with insignificant overheads in terms of area

Published in:

2007 Design, Automation & Test in Europe Conference & Exhibition

Date of Conference:

16-20 April 2007