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SoC Testing Using LFSR Reseeding, and Scan-Slice- Based TAM Optimization and Test Scheduling

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3 Author(s)
Zhanglei Wang ; ECE Dept., Duke Univ., Durham, NC ; Chakrabarty, K. ; Seongmoon Wang

We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as the compression engine. All cores on the SoC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the core bits from the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that tries to maximize the number of core bits the LFSR can produce at each clock cycle, such that the overall test application time is minimized. Experimental results for both ISCAS circuits and industrial circuits show that optimal test application time, which is determined by the largest core, can be achieved. The proposed approach has small hardware overhead and is easy to deploy. Only one LFSR, one phase shifter, and a few counters should be added to the SoC. The scheduling algorithm is also scalable for large industrial circuits. The CPU time for a large industrial design ranges from 1 to 30 minutes

Published in:

Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07

Date of Conference:

16-20 April 2007

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