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Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling

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2 Author(s)
Quming Zhou ; Dept. of Electrical and Computer Engg., Rice University, Houston, TX, USA, ; Kedarnath J. Balakrishnan

A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed in this paper. A broadcast scan based test compression algorithm for parallel testing of cores with multiple scan chains is used to reduce the test data of the SoC. Unlike other test compression schemes, the proposed algorithm doesn't require specialized test generation or fault simulation and is applicable with intellectual property (IP) cores. The core testing schedule with compression enabled is decided using a generalized strip packing algorithm. The hardware architecture to implement the proposed scheme is very simple. By using the combined approach, the total test data volume and test application time of the SoC is reduced to a level comparable with the test data volume and test application time of the largest core in the SoC

Published in:

2007 Design, Automation & Test in Europe Conference & Exhibition

Date of Conference:

16-20 April 2007