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Maximum-speed s.t.t. state assignments for sequential machines

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2 Author(s)
Burton, D.P. ; University of Birmingham, Department of Electronic & Electrical Engineering, Birmingham, UK ; Noaks, D.R.

A systematic procedure for deriving single-transition-time (s.t.t.) state assignments yielding maximum-speed as chronous machines is described. The delay between applying an input and achieving a stable state is two gate delays for all cases.

Published in:

Electronics Letters  (Volume:4 ,  Issue: 21 )