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TAM Design and Optimization for Transparency-Based SoC Test

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5 Author(s)
Yoneda, T. ; Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Kansai ; Shuto, A. ; Ichihara, H. ; Inoue, T.
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We present a graph model and an ILP model for optimal TAM design for transparency-based SoC testing. The proposed method is an extension of (Chakrabarty, 2003) so that not only the system-level cost but also the core-level cost can be simultaneously taken into consideration during the optimization process. We also relax the constraints by considering test dataflows and extend it to be able to handle the case where cores cannot be made transparent due to IP protection. The proposed ILP model can represent various problems including the same problem as (Chakrabarty, 2003) and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to (Chakrabarty, 2003).

Published in:

VLSI Test Symposium, 2007. 25th IEEE

Date of Conference:

6-10 May 2007

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